Building a NAND flash controller with high-level synthesis
In this article, we describe how we were able to apply a commercial HLS tool (Cadence C-to-Silicon Compiler) to a NAND flash controller with an error correction code (ECC) block. The initial ECC design was based on an ECC software program, which led to a large area due to two large arrays. We then used our domain knowledge of the ECC coding theorem to structure the code for hardware implementation.
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