While looking for news on models I started talking to Kurt Shuler, Vice President of Marketing at Arteris. Arteris just did an announcement together with Synopsys (link to press release). During my discussion with Kurt I asked him about Arteris’ transaction-level models and how customers use these models.
Tom: Can you explain what Arteris does?
Kurt: Arteris is a semiconductor IP vendor that supplies SoC interconnect IP and chip-to-chip interface IP to SoC makers. Our interconnect IP product, Arteris FlexNoC, is highly configurable because it must adapt to all the IP the SoC designer includes within his SoC, and also adapt to the SoC’s performance and QoS requirements.
Our differentiating technology provides a commercial interconnect solution based on network-on-chip (NoC) technology. When I say NoC, I mean that we packetize data that enters the interconnect. This allows the SoC architect to then determine the bit widths of the paths that the data will take through the interconnect. This reduces the number of wires in the interconnect, and allows the small, distributed elements of the NoC interconnect to be easily squeezed within the “white space” between IP blocks within the SoC floorplan.
Tom: Who are your main customers?
Kurt: Our major customers are Qualcomm, Samsung and Texas Instruments. They use our interconnect IP for their flagship SoC products because it helps reduce design cycle time, shrink die size, and decrease power consumption.
Tom: What type of transaction-level models does Arteris make available to its customers?
Kurt: Within our FlexNoC interconnect IP tooling we have a feature called FlexExplorer which can create SystemC TLM-2.0 models at three levels of abstraction:
- Architect’s View: approximately timed – AT
- Verification View: cycle accurate-CA
- Programmer’s View: loosely timed-LT
Tom: What are customers using the models for?
Kurt: SoC designer end-users want to reduce the design cycle time. To achieve this goal customers want to explore the influence of interconnect configuration options as early as possible in the design cycle and study the impact of different variants to find the configuration that best meets
Tom: How does the typical TLM flow work?
Kurt: Within Arteris FlexNoC’s FlexExplorer “cockpit”, architects are using the SystemC models to quickly define an SoC interconnect configuration (specification, architecture, topology and QoS) that looks like it will meet product requirements. Then, architects can import the SystemC models available from FlexExplorer into Synopsys Platform Architect MCO to perform simulation and performance analysis in the context of the entire system, using other SystemC models to represent “the rest of the SoC” beyond the interconnect. This makes for a finer degree of realism to modify the interconnect configuration created in FlexNoC.
Tom: What are the advantages of this TLM interoperability?
Kurt: Our integration with Platform Architect allows the SoC designer to have an SoC- or system-centric “macro” view of the SoC included in his/her decision making earlier in the design cycle. It builds upon the existing interconnect-centric (“micro” view) capabilities of FlexNoC and FlexExplorer by allowing more realistic system level and SoC level simulation than what can be done within FlexExplorer alone, and providing a great “cockpit” with which to visualize and understand the resulting data from a simulation.
Tom: How do customers know that the architecture exploration tasks they do using your models relate to the actual implementation?
Kurt: The models outputted from FlexNoC are automatically 100% comparable by construction with the RTL.
Thanks Kurt for this interview.
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