So TLMCentral is all about transaction-level models … But are those models really worth the effort? I guess I wouldn’t be writing a blog called “All Models, All The Time…” if I didn’t think they were. And did you know you can recycle and reuse models?  For example, besides the most obvious value proposition – to enable virtual prototyping, transaction-level models can have value in verifying their RTL counterparts.

 Let’s first recap the requirements for model development. Virtual prototyping offers software developers with a methodology to start software development early in the design cycle. The extra visibility, debugability and controllability eases and speeds up complex software development tasks like OS porting and driver development. But the basis for this virtual prototyping paradigm shift is, of course, the availability of the right SystemC models to enable all the advanced capabilities that virtual prototyping tools have to offer. The requirements for this type of model seem quite steep to meet: enable high simulation speed, full visibility and controllability and provide an accurate programmer’s view of the actual IP. Last but not least, the model needs to be available long before the RTL is ready.

Yet it is not impossible to meet these requirements and still achieve higher ROI, not only from a software development point of view, but also from an IP block design aspect. High-level models can speed up development of testbenches and hence reduce the verification effort of the actual RTL model.

To verify the models we can build a simple virtual prototype running software to interact with and test the correct functionality of the IP model. Based on the embedded verification plan directed tests can be defined and run to achieve the right coverage and check if no assertions are being triggered.

Example of UART TLM model verification:

This test suite can be reused later to verify the RTL model of the IP. Not only does this reduce the development time of the RTL model as it can be verified against a golden reference model, the time to create the test suite is smaller as it can be done using a fast simulation infrastructure with powerful debug capabilities. And last but not least, the methodology improves overall IP model quality as the verification can be done in the context of a relevant system running a relevant set of software stacks, including booting an OS.

Example of how the UART RTL model can be verified reusing the testbench from the TLM model:

So as you can see transaction-level modeling can be green as well. Let’s reduce the IP modeling and verification effort, reuse testbenches and recycle existing models to create derivative ones.